In digital signal processing applications, it may be desired to implement an integer divide function in the hardware of a digital circuit to perform specific function. In a typical application, a divider circuit is included in a portion of an AM receiver. A digital to analog converter in the receiver samples a received signal and a reference signal at a certain rate, and the divider performs a normalization operation by dividing the received input signal by the reference signal. The division operation is continuous (real time) and is performed within a portion of the sampling period. The received signal constitutes the numerator input N and the reference signal constitutes the denominator input D of the divider. However, the result of a division operation may not be an exact value, and a certain error may be present in the resulting quotient.
FIG. 1 shows a conventional 4 bit by 4 bit divider circuit, which divides, using repeated subtraction, a four-digit dividend X represented by bits X3-X0 by a divisor Y represented by Y3-Y0. The dividend X is loaded into a register 90 via buffers 61, 62, 63, and 64 of a tri-state buffer device 60, having a control input 15. The control input 15, in association with circuitry shown in block 80, allows the dividend X to be loaded in to register 90 only in the initial step of the division operation. The register 90 consists of four type-D flip flops 11, 12, 13, and 14 having outputs Q0, Q1, Q2, and Q3 coupled to first inputs A0, A1, A2, and A3 respectively of a four bit full adder 20. The divisor Inputs Y3-Y0 are coupled to inverters 31, 32, 33, and 34 of an inverting device 30, and will produce the ones complement of the divisor Y. The outputs of the inverting device 30 are coupled to second inputs B0, B1, B2, and B3 of the adder 20. The output of an AND gate 40 is coupled to clock input of the register 90, while inputs of the AND gate 40 are coupled to carry output C2 of the adder 20, and a clock signal 25. Carry input C1 of the adder 20 is set to a logic 1 , in order to produce a two complete of the Y input. The output of the AND gate 40 is coupled to a 4-bit counter 50 having an output Z, represented by Z3-Z0. The counter 50 has an initial setting of 0, after dividend X is loaded in to register 90.
Assuming that X&gt;Y, the C2 output initially will be set to 1, and hence the AND gate 40 is enabled. The difference X-Y appears at outputs S3, S2, S1, and S0 of the adder 20. After closing the clock switch 70, the first clock pulse will load the difference X-Y into the register, and will also advance the counter 50 by one step. The numeric output of the adder 20 will be equal to [(X-Y)-Y], or (X-2Y). If C2 is still a logic 1, the AND gate 40 will be enabled and the second clock pulse will load X-2Y into the register and advance the counter a second step. If after n clock pulses the remainder becomes less than Y, then C2 becomes a logic 0. The AND gate 40 will now be disabled and the counter 50 will stop. Hence the quotient Z is read from the counter.
In some digital signal processing circuits, it is necessary to perform the division operation within one clock cycle. The divider circuit 10 operates in a sequential mode, therefore it is not desirable in applications, wherein division speed is critical.
Furthermore, in a digital division operation of two integer binary numbers the result is truncated, in order to provide an integer quotient. However, for the purpose of normalizing amplitudes of signals, it is desirable to have a relatively constant error over a wide range of input amplitudes.
Another disadvantage of a sequential circuit, such as the divider 10, is that it consumes more power than an equivalent combinational logic circuit. This is primarily due to multiple clocking nature of the divider 10.